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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 ad5308/AD5318/ad5328 * 2.5 v to 5.5 v octal voltage output 8-/10-/12-bit dacs in 16-lead tssop functional block diagram buffer input register dac register interface logic din ldac gnd v out b v out c v out d v out e v out g v out h v out f v dd power-on reset gain-select logic v out a v ref efgh v ref abcd sync sclk power-down logic gain-select logic string dac b buffer input register dac register string dac c buffer input register dac register string dac d buffer input register dac register string dac e buffer input register dac register buffer input register dac register buffer input register dac register buffer input register dac register v dd v dd ldac string dac f string dac g string dac h string dac a general description the ad5308/AD5318/ad5328 are octal 8-, 10-, and 12-bit buffered voltage output dacs in a 16-lead tssop package. they operate from a single 2.5 v to 5.5 v supply consuming 0.7 ma typ at 3 v. their on-chip output amplifiers allow the out puts to swing rail to rail with a slew rate of 0.7 v/ s. the ad5308/ AD5318/ad5328 use a versatile 3-wire serial inter face that operates at clock rates up to 30 mhz and is compatible with stan- dard spi, qspi, microwire, and dsp interface standards. the references for the eight dacs are derived from two refer- ence pins (one per dac quad). these reference inputs can be configured as buffered, unbuffered, or v dd inputs. the parts incorporate a power-on reset circuit that ensures that the dac outputs power up to 0 v and remain there until a valid write to the device takes place. the outputs of all dacs may be updated simultaneously using the asynchronous ldac input. the parts contain a power-down feature that reduces the current consump- tion of the devices to 400 na @ 5 v (120 na @ 3 v). the eight channels of the dac may be powered down individually. all three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board. * protected by u.s. patent no. 5,969,657; other patents pending. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. features ad5308: eight buffered 8-bit dacs in 16-lead tssop AD5318: eight buffered 10-bit dacs in 16-lead tssop ad5328: eight buffered 12-bit dacs in 16-lead tssop low power operation: 0.7 ma @ 3 v guaranteed monotonic by design over all codes power-down to 120 na @ 3 v, 400 na @ 5 v double-buffered input logic buffered/unbuffered/v dd reference input options output range: 0? ref or 0? v ref power-on reset to zero volts programmability individual-channel power-down simultaneous update of outputs ( ldac ) low power, spi, qspi, microwire, and dsp- compatible 3-wire serial interface on-chip rail-to-rail output buffer amplifiers temperature range ?0 o c to +105 o c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources optical networking automatic test equipment mobile comms programmable attenuators industrial process control
rev. 0 e2e ad5308/AD5318/ad5328especifications b version 2 parameter 1 min typ max unit conditions/comments dc performance 3, 4 ad5308 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes AD5318 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.50 lsb guaranteed monotonic by design over all codes ad5328 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.2 1.0 lsb guaranteed monotonic by design over all codes offset error 5 60 mv v dd = 4.5 v, gain = +2; see figures 2 and 3. gain error 0.30 1.25 % of fsr v dd = 4.5 v, gain = +2; see figures 2 and 3. lower dead band 5 10 60 mv see figure 2. lower dead band exists only if offset error is negative. upper dead band 5 10 60 mv see figure 3. upper dead band exists only if v ref = v dd and offset plus gain error is positive. offset error drift 6 e12 ppm of fsr/ c gain error drift 6 e5 ppm of fsr/ c dc power supply rejection ratio 6 e60 db v dd = 10% dc crosstalk 6 200 vr l = 2 k to gnd or v dd dac reference inputs 6 v ref inpu t range 1.0 v dd vb uffered reference mode 0.25 v dd v unbuffered reference mode v ref input impedance (r dac ) >10.0 m buffered reference mode and power-down mode 37.0 45.0 k unbuffered reference mode. 0ev ref output range. 18.0 22.0 k unbuffered reference mode. 0e2 v ref output range. reference feedthrough e70.0 db frequency = 10 khz channel-to-channel isolation e75.0 db frequency = 10 khz output characteristics 6 minimum output voltage 7 0.001 v this is a measure of the minimum and maximum drive maximum output voltage 7 v dd e 0.001 v capability of the output amplifier. dc output impedance 0.5 short circuit current 25.0 ma v dd = 5 v 16.0 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode. v dd = 5 v. 5.0 s coming out of power-down mode. v dd = 3 v. logic inputs 6 input current 1 a v il , input low voltage 0.8 v v dd = 5 v 10% 0.8 v v dd = 3 v 10% 0.7 v v dd = 2.5 v v ih , input high voltage 1.7 v v dd = 2.5 v to 5.5 v; ttl and cmos compatible pin capacitance 3.0 pf power requirements v dd 2.5 5.5 v i dd (normal mode) 8 v ih = v dd and v il = gnd v dd = 4.5 v to 5 .5 v 1.0 1.8 ma all dacs in unbuffered mode. in buffered mode, extra v dd = 2.5 v to 3.6 v 0.7 1.5 ma current is typically x a per dac; x = (5 a + v ref /r dac )/4. i dd (power-down mode) 9 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.4 1 a v dd = 2.5 v to 3.6 v 0.12 1 a (v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted.) notes 1 see terminology section. 2 temperature range: b version: e40 c to +105 c; typical at 25 c. 3 dc specifications tested with the outputs unloaded unless stated otherwise. 4 linearity is tested using a reduced code range: ad5308 (code 8 to code 255), AD5318 (code 28 to code 1023), and ad5328 (code 11 5 to code 4095). 5 this corresponds to x codes. x = dead band voltage/lsb size. 6 guaranteed by design and characterization; not production tested. 7 for the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its max imum voltage, v ref = v dd and offset plus gain error must be positive. 8 interface inactive. all dacs active. dac outputs unloaded. 9 all eight dacs powered down. specifications subject to change without notice.
rev. 0 ad5308/AD5318/ad5328 e3e sclk sync din db15 db0 ldac 1 ldac 2 notes 1 asynchronous ldac update mode 2 synchronous ldac update mode t 1 t 2 t 8 t 3 t 4 t 5 t 6 t 9 t 11 t 7 t 10 figure 1. serial interface timing diagram specifications ac characteristics 1 b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5308 6 8 s 1/4 scale to 3/4 scale change (40 hex to c0 hex) AD5318 7 9 s 1/4 scale to 3/4 scale change (100 hex to 300 hex) ad5328 8 10 s 1/4 scale to 3/4 scale change (400 hex to c00 hex) slew rate 0.7 v/ s major-code change glitch energy 12 nv sec 1 lsb c hange around major carry digital feedthrough 0.5 nv sec digital crosstalk 0.5 nv sec analog crosstalk 1 nv sec dac-to-dac crosstalk 3 nv sec multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p. unbuffered mode. total harmonic distortion e70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz. notes 1 guaranteed by design and characterization; not production tested. 2 see terminology section. 3 temperature range: b version: e40 c to +105 c; typical at +25 c. specifications subject to change without notice. timing characteristics 1, 2, 3 b version parameter limit at t min , t max unit conditions/comments t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 50 ns min minimum sync high time t 9 20 ns min ldac pulsewidth t 10 20 ns min sclk falling edge to ldac rising edge t 11 0 ns min sclk falling edge to ldac falling edge notes 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figures 2 and 3. specifications subject to change without notice. (v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted.)
rev. 0 e4e ad5308/AD5318/ad5328 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5308/AD5318/ad5328 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v digital input voltage to gnd . . . . . . . e0.3 v to v dd + 0.3 v reference input voltage to gnd . . . . e0.3 v to v dd + 0.3 v v out aev out d to gnd . . . . . . . . . . . e0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . e40 c to +105 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature (t j max ) . . . . . . . . . . . . . . . . . . 150 c 16-lead tssop package power dissipation . . . . . . . . . . . . . . . . . . (t j max e t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . 150.4 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . 220 5 c time at peak temperature . . . . . . . . . . 10 sec to 40 sec notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide model temperature range package description package option ad5308bru e40 c to +105 ct hin shrink small outline package (tssop) ru-16 AD5318bru e40 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5328bru e40 c to +105 ct hin shrink small outline package (tssop) ru-16
rev. 0 ad5308/AD5318/ad5328 e5e pin function descriptions pin no. mnemonic function 1 ldac this active low-control input transfers the contents of the input registers to their respective dac registers. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied permanently low. 2 sync active low-control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the following 16 clocks. if sync is taken high before the 16th falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 3v dd power supply input. these parts can be operated from 2.5 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4v out ab uffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 5v out bb uffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 6v out cb uffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 7v out db uffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 8v ref abcd reference input pin for dacs a, b, c, and d. it may be configured as a buffered, unbuffered, or v dd input to the four dacs, depending on the state of the buf and v dd control bits. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 9v ref efgh reference input pin for dacs e, f, g, and h. it may be configured as a buffered, unbuffered, or v dd input to the four dacs, depending on the state of the buf and v dd control bits. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 10 v out eb uffered analog output voltage from dac e. the output amplifier has rail-to-rail operation. 11 v out fb uffered analog output voltage from dac f. the output amplifier has rail-to-rail operation. 12 v out gb uffered analog output voltage from dac g. the output amplifier has rail-to-rail operation. 13 v out hb uffered analog output voltage from dac h. the output amplifier has rail-to-rail operation. 14 gnd ground reference point for all circuitry on the part. 15 din serial data input. this device has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. the din input buffer is powered down after each write cycle. 16 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. the sclk input buffer is powered down after each write cycle. pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sync ldac v dd v out a v out b v out c v out d v ref abcd sclk din v out e ad5308/ AD5318/ ad5328 v ref efgh v out f v out g v out h gnd
rev. 0 e6e ad5308/AD5318/ad5328 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. typical inl versus code plots can be seen in tpcs 1, 2, and 3. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl versus code plots can be seen in tpcs 4, 5, and 6. offset error this is a measure of the offset error of the dac and the output amplifier (see figures 2 and 3). it can be negative or positive, and is expressed in mv. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift t his is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is mea sured in dbs. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in v. reference feedthrough t his is the ratio of the amplitude of the signal at the dac o utput to the reference input when the dac output is not being updated (i.e., ldac is high). it is expressed in dbs. channel-to-channel isolation this is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in dbs. major-code transition glitch energy m ajor-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital code is changed by 1 lsb at the major carry transition (011 ...11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, b ut is measured when the dac is not being written to the ( sync held high). it is specified in nv secs and is measured with a full- scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv secs. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change ( all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv secs. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac d ue to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv secs. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion t his is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference f or the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in dbs.
rev. 0 ad5308/AD5318/ad5328 e7e gain error and offset error output voltage negative offset error dac code negative offset error amplifier footroom lower dead band codes actual ideal figure 2. transfer function with negative offset (v ref = v dd ) output voltage positive offset error dac code gain error and offset error actual ideal upper dead band codes full scale figure 3. transfer function with positive offset
rev. 0 e8e ad5308/AD5318/ad5328 code inl error e lsbs 1.0 0.5 e1.0 0 50 250 100 150 200 0 e0.5 t a = 25 c v dd = 5v tpc 1. ad5308 typical inl plot code dnl error e lsbs 050 250 100 150 200 e0.1 e0.2 e0.3 0.3 0.1 0.2 0 t a = 25 c v dd = 5v tpc 4. ad5308 typical dnl plot v ref e v error e lsbs 0.5 0.25 e0.5 01 5 234 0 e0.25 v dd = 5v t a = 25 c max inl max dnl min dnl min inl tpc 7. ad5308 inl and dnl error vs. v ref code inl error e lsbs 3 0 200 1000 400 600 800 0 e1 e2 e3 2 1 t a = 25 c v dd = 5v tpc 2. AD5318 typical inl plot code dnl error e lsbs 0.4 e0.4 600 400 800 1000 0 e0.6 0.6 0.2 e0.2 t a = 25 c v dd = 5v 200 0 tpc 5. AD5318 typical dnl plot temperature e c error e lsbs 0.5 0.2 e0.5 40 0 40 0 e0.2 v dd = 5v v ref = 3v max inl 80 120 e0.4 e0.3 e0.1 0.1 0.3 0.4 max dnl min inl min dnl tpc 8. ad5308 inl error and dnl error vs. temperature code inl error e lsbs 12 0 e4 e8 8 4 0 4000 1000 2000 3000 e12 t a = 25 c v dd = 5v tpc 3. ad5328 typical inl plot code dnl error e lsbs 0.5 2000 3000 4000 0 e1 1 e0.5 t a = 25 c v dd = 5v 1000 0 tpc 6. ad5328 typical dnl plot gain error temperature e c error e % fsr 1 0.5 e1 40 0 40 0 e0.5 v dd = 5v v ref = 2v offset error 80 120 tpc 9. ad5308 offset error and gain error vs. temperature etypical performance characteristics
rev. 0 ad5308/AD5318/ad5328 e9e gain error v dd e v error e % fsr 0.2 e0.6 01 3 0 e0.4 t a = 25 c v ref = 2v 46 e0.5 e0.3 e0.2 e0.1 0.1 25 offset error tpc 10. offset error and gain error vs. v dd supply voltage e v i dd e a 1.3 0.6 0.7 0.9 1.0 2.0 1.2 1.1 0.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t a = 25 c v ref = 2v, gain = +1, unbuffered v ref = v dd , gain = +1, unbuffered v ref = 2v, gain = +1, buffered v ref = v dd tpc 13. supply current vs. supply voltage v out a 5s ch1 ch2 sclk t a = 25 c v dd = 5v v ref = 5v ch1 1v, ch2 5v, time base= 1 s/div tpc 16. half-scale settling (1/4 to 3/4 scale code change) 5v source sink/source current e ma v out e v 5 0 01 3 4 46 1 2 3 25 3v source 3v sink 5v sink tpc 11. v out source and sink current capability v dd e v i dd power-down e a 1.0 0 0.8 0.2 0.4 0.6 2.0 0.9 0.7 0.1 0.3 0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t a = 25 c tpc 14. power-down current vs. supply voltage v out a t a = 25 c v dd = 5v v ref = 2v ch1 ch2 ch1 2.00v, ch2 200mv, time base = 200 s/div v dd tpc 17. power-on reset to 0 v dac code i dd e a 1.0 zero scale full scale 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 half scale v dd = 5v t a = 25 c tpc 12. supply current vs. dac code v logic e v i dd e a 0.6 0 1.0 0.7 0.8 1.0 1.2 1.4 2.0 3.0 4.0 t a = 25 c v dd = 5v decreasing v dd = 3v increasing 0.9 1.1 1.3 1.5 2.5 3.5 0.5 4.5 5.0 tpc 15. supply current vs. logic input voltage for sclk and din increasing and decreasing t a = 25 c v dd = 5v v ref = 2v ch1 ch2 ch1 500mv, ch2 5.00v, time base = 1 s/div v out a pd tpc 18. exiting power-down to midscale
rev. 0 e10e ad5308/AD5318/ad5328 i dd e ma frequency 0.6 35 30 25 20 15 10 5 0 0.7 0.8 0.9 1.0 1.1 mean: 0.693798 mean: 1.02055 ss = 300 v dd = 3v v dd = 5v tpc 19. i dd histogram with v dd = 3 v and v dd = 5 v v dd = 5v t a = 25 c v ref e v full-scale error e v 0.02 e0.02 01 3 0.01 e0.01 46 0 25 tpc 22. full-scale error vs. v ref 1 s/div 2.48 2.49 v out e v 2.47 2.50 tpc 20. ad5328 major-code transition glitch energy 100ns/div 1mv/div tpc 23. dac-to-dac crosstalk frequency e khz 10 e40 0.01 e20 e30 0 e10 db 0.1 1 10 100 1000 10000 e50 e60 tpc 21. multiplying bandwidth (small-signal frequency re sponse)
rev. 0 ad5308/AD5318/ad5328 e11e functional description the ad5308/AD5318/ad5328 are octal resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits respectively. each contains eight output buffer amplifiers and is written to via a 3-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifi- ers provide rail-to-rail output swing with a slew rate of 0.7 v/ s. dacs a, b, c, and d share a common reference input, namely v ref abcd. dacs e, f, g, and h share a common reference input, namely v ref efgh. each reference input may be buff- ered to draw virtually no current from the reference source, may be unbuffered to give a reference input range from 0.25 v to v dd , or come from v dd . the devices have a power-down mode in which all dacs may be turned off individually with a high impedance output. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the corre- sponding dac. figure 4 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by: v vd out ref n = 2 where d = the decimal equivalent of the binary code that is loaded to the dac register; 0e255 for ad5308 (8 bits) 0e1023 for AD5318 (10 bits) 0e4095 for ad5328 (12 bits) n = the dac resolution v out a gain mode (gain = 1 or 2) v ref abcd buf dac register input register resistor string output buffer amplifier reference buffer v dd v dd figure 4. single dac channel architecture resistor string the resistor-string section is shown in figure 5. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. to output amplifier r r r r r figure 5. resistor string dac reference inputs there is a reference pin for each quad of dacs. the reference inputs can be buffered from v dd, or unbuffered. the advantage with the buffered input is the high impedance it presents to the voltage source driving it. however, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 v and as high as v dd since there is no restriction due to the headroom and footroom of the reference amplifier. if there is a buffered reference in the circuit (e.g., ref192), there is no need to use the on-chip buffers of the ad5308/ AD5318/ad5328. in unbuffered mode, the input impedance is still large at typically 45 k per reference input for 0ev ref mode and 22 k for 0e2 v ref mode. output amplifier the output buffer amplifier is capable of generating output voltages to w ithin 1 mv of either rail. its actual range depends on the value of v ref , the gain of the output amplifier, the offset error, and the gain error. if a gain of 1 is selected (gain bit = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain bit = 1), the output range is 0.001 v to 2 v ref . because of clamping, however, the maximum output is limited to v dd e 0.001 v. the output amplifier is capable of driving a load of 2 k to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in tpc 11. the slew rate is 0.7 v/ s with a half-scale settling time to 0.5 lsb (at 8 bits) of 6 s. power-on reset t he ad5308/AD5318/ad5328 are provided with a power-on reset function so that they power up in a defined state. the power-on state is: n ormal operation r eference inputs unbuffered 0ev ref output range o utput voltage set to 0 v l dac bits set to ldac high both input and dac registers are filled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up.
rev. 0 e12e ad5308/AD5318/ad5328 serial interface the ad5308/AD5318/ad5328 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 mhz a nd is compatible with spi, qspi, microwire, and dsp in terface standards. input shift register the input shift register is 16 bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this operation is shown in figure 1. the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can only be trans- ferred into the device while sync is low. to start the serial data transfer, sync should be taken low, observing the mini- mum sync to sclk falling edge setup time, t 4 . after sync goes low, serial data will be shifted into the device?s input shift register on the falling edges of sclk for 16 clock pulses. to end the transfer, sync must be taken high after the falling edge of the 16th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected dac. if sync is taken high before the 16th falling edge of sclk, the data transfer will be aborted and the dac input registers will not be updated. data is loaded msb first (bit 15). the first bit determines whether it is a dac write or a control function. dac write here, the 16-bit word consists of one control bit and three address bits followed by 8, 10, or 12 bits of dac data, depend- ing on the device type. in the case of a dac write, the msb will be a 0. the next three address bits determine whether the data is for dac a, dac b, dac c, dac d, dac e, dac f, dac g, or dac h. the ad5328 uses all 12 bits of dac data. the AD5318 uses 10 bits and ignores the 2 lsbs. the ad5308 uses 8 bits and ignores the last 4 bits. these ignored lsbs should be set to 0. the data format is straight binary, with all zeros corresponding to 0 v output and all ones corresponding to full-scale output. table i. address bits for the ad53x8 a2 (bit 14) a1 (bit 13) a0 (bit 12) dac addressed 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 0 0 dac e 1 0 1 dac f 1 1 0 dac g 1 1 1 dac h control functions in the case of a control function, the msb (bit 15) will be a 1. this is followed by two control bits, which determine the mode. there are four different control modes, each of which is described below. the write sequences for these modes are shown in table ii. reference and gain mode this mode determines whether the reference for each group of dacs is buffered, unbuffered, or from v dd . it also determines the gain of the output amplifier. to set up the reference of both groups, set the control bits to (00), set the gain bits, set the buf bits, and set the v dd bits. buf: controls whether the reference of a group of dacs is buffered or unbuffered. the reference of the first group of dacs (a, b, c, and d) is controlled by setting bit 2, and the second group of dacs (e, f, g, and h) is controlled by setting bit 3. 0: unbuffered reference 1: buffered reference gain: the gain of the dacs is controlled by setting bit 4 for the first group of dacs (a, b, c, and d) and bit 5 for the second group of dacs (e, f, g, and h). 0: output range of 0ev ref 1: output range of 0e2 v ref d /c a0 d7 d6 d5 d4 d3 d2 d1 d0 0000 bit 0 (lsb) bit 15 (msb) data bits a1 a2 figure 6. ad5308 input shift register contents data bits a0 00 bit 0 (lsb) bit 15 (msb) a1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a2 d /c figure 7. AD5318 input shift register contents data bits d /c a0 bit 0 (lsb) bit 15 (msb) a1 a2 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 figure 8. ad5328 input shift register contents
rev. 0 ad5308/AD5318/ad5328 e13e table ii. control words for the ad53x8 d cc (gain bits) (buf bits) (v dd bits) gain of output amplifier 10 0x xx xxxx e..h a..d e..h a..d e..h a..d and reference selection ( ldac bits ) 10 1x xx xxxx x x x x 1/0 1/0 ldac (channels) 11 0x x x x x h g f e d c b a power-down (reset) 11 1 1/0 xx xxxx x x x x x x r eset on completion of this write sequence, the channels that have been set to 1 are powered down. reset mode this mode consists of two possible reset functions, as outlined in table iv. table iv. reset mode bit bit bit bit bit 15 14 13 12 11 .... 0 description 1 1 1 0 x .... x dac data reset 1 1 1 1 x .... x data and control reset dac data reset: on completion of this write sequence, all dac registers and input registers are filled with zeros. data and control reset: this function carries out a dac data reset and also resets all the control bits (gain, buf, v dd , ldac, and power-down channels) to their power-on conditions. low-power serial interface to minimize the power consumption of the device, the interface only powers up fully when the device is being written to, i.e., on the falling edge of sync . the sclk and din input buffers are powered down on the rising edge of sync . load dac input ( ldac c adac ldac ldac ldac ralldac ralldacd ldacc ldac dd dd dacacd dd dac dd dd r a ldac mode ldac mode controls ldac , which determines when data is transferred from the input registers to the dac registers. there are three options when updating the dac registers, as shown in table iii below. table iii. ldac ldac ldac ldac ldac d ldac l ldac ldac r ldac low: (00) this sets ldac permanently low, thus allow- ing the dac registers to be updated continuously. ldac high: (01) this sets ldac permanently high. the dac registers are latched, and the input registers may change without affecting the contents of the dac registers. this is the default option for this mode. ldac single update: (10) this causes a single pulse on ldac dac reserved: (11) reserved. power-down mode the individual channels of the ad5308/AD5318/ad5328 can be powered down separately. the control mode for this is (10).
rev. 0 e14e ad5308/AD5318/ad5328 if the user wishes to update the dac through software, then the ldac pin should be tied high and the ldac mode bits set as required. alternatively, if the user wishes to control the dac through hardware, i.e., the ldac pin, then the ldac mode bits should be set to ldac high (default mode). use of the ldac function enables double buffering of the dac data, and the gain, buf and v dd bits. there are two ways in which the ldac function can operate: synchronous ldac : the dac registers are updated after new data is read in on the falling edge of the 16th sclk pulse. ldac can be permanently low or pulsed as in figure 1. asynchronous ldac : the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. double-buffered interface the ad5308/AD5318/ad5328 dacs all have double-buffered interfaces consisting of two banks of registers: input and dac. the input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac regis- ters contain the digital code used by the resistor strings. when the ldac pin is high, and the ldac bits are set to (01), the dac registers are latched, and the input registers may change state without affecting the contents of the dac registers. however, when the ldac bits are set to (00) or when the ldac pin is brought low, the dac registers become transpar- ent and the contents of the input registers are transferred to them. the double-buffered interface is useful if the user requires simultaneous updating of all dac outputs. the user may write to seven of the input registers individually and then, by bringing ldac low when writing to the remaining dac input register, all outputs will update simultaneously. these parts contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5308/AD5318/ad5328, the part will only update the dac register if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down mode the ad5308/AD5318/ad5328 have low-power consumption, typically dissipating 2.4 mw with a 3 v supply and 5 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power-down mode, which was described previously. when in default mode, all dacs work normally with a typical power consumption of 1 ma at 5 v (800 a at 3 v). however, when all dacs are powered down, i.e., in power-down mode, the supply current falls to 400 na at 5 v (120 na at 3 v). not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier making it open-circuit. this has the advantage that the output is three- state, while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illustrated in figure 10. the bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. in fact, it is possible to load new data to the input registers and dac registers during power-down. the dac outputs will update as soon as the device comes out of power-down mode. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. resistor- string dac power-down circuitry amplifier v out figure 10. output stage during power-down microprocessor interfacing adsp-2101/adsp-2103 to ad5308/AD5318/ad5328 interface figure 11 shows a serial interface between the ad5308/ AD5318/ad5328 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/ adsp-2103 sport is programmed through the sport con trol register and should be configured as follows: internal clock operation, active-low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the dsp?s serial clock and clocked into the ad5308/ AD5318/ad5328 on the falling edge of the dac?s sclk. ad5308/ AD5318/ ad5328 * sclk din sync tfs dt sclk adsp-2101/ adsp-2103 * * additional pins omitted for clarity figure 11. adsp-2101/adsp-2103 to ad5308 AD5318/ad5328 interface 68hc11/68l11 to ad5308/AD5318/ad5328 interface figure 12 shows a serial interface between the ad5308/AD5318/ ad5328 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5308/AD5318/ ad5328, while the mosi output drives the serial data line (din) of the dac. the sync signal is derived from a port line (pc7). the setup conditions for the correct operation of this interface are as f ollows: the 68hc11/68l11 should be configured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). w hen the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with o nly eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5308/AD5318/ad5328, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure.
rev. 0 ad5308/AD5318/ad5328 e15e din sclk sync pc7 sck mosi 68hc11/68l11 * * additional pins omitted for clarity ad5308/ AD5318/ ad5328 * figure 12. 68hc11/68l11 to ad5308/AD5318/ ad5328 interface 80c51/80l51 to ad5308/AD5318/ad5328 interface figure 13 shows a serial interface between the ad5308/AD5318/ ad5328 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5308/AD5318/ad5328, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case, port line p3.3 is used. when data is transmitted to the ad5308/AD5318/ad5328, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in a format that has the lsb first. the ad5308/AD5318/ad 5328 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. din sclk sync p3.3 txd rxd 80c51/80l51 * * additional pins omitted for clarity ad5308/ AD5318/ ad5328 * figure 13. 80c51/80l51 to ad5308/AD5318/ ad5328 interface microwire to ad5308/AD5318/ad5328 interface figure 14 shows an interface between the ad5308/AD5318/ ad5328 and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the ad5308/AD5318/ad5328 on the rising edge of sk, which corresponds to the falling edge of the dac?s sclk. din sclk sync cs sk so microwire * * additional pins omitted for clarity ad5308/ AD5318/ ad5328 * figure 14. microwire to ad5308/AD5318/ ad5328 interface applications typical application circuit the ad5308/AD5318/ad5328 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 v to v dd . more typically, these devices are used with a fixed, precision reference voltage. suitable references for 5 v operation are the ad780, adr381, and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ad589 and ad1580 (1.2 v band gap references). figure 15 shows a typical setup for the ad5308/AD5318/ad5328 when using an external reference. 1 f v ref abcd v ref efgh v out v in 0.1 f 10 f sclk din sync gnd v out a ad5308/AD5318/ ad5328 serial interface ad780/adr3811/ref192 with v dd = 5v or ad589/ad1580 with v dd = 2.5v v out b v dd = 2.5v to 5.5v ext ref v out h v out g figure 15. ad5308/AD5318/ad5328 using a 2.5 v external reference driving v dd from the reference voltage if an output range of 0 v to v dd is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to v dd . as this supply may be noisy and not very accurate, the ad5308/AD5318/ad5328 may be powered from a voltage reference. for example, using a 5 v reference, such as the ref195, will work because the ref195 will output a steady supply voltage for the ad5308/AD5318/ ad5328. the typical current required from the ref195 is a 1 a supply current and 112 a into the reference inputs (if unbuffered); this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k load on each output) is: 1.22 ma + 8(5 v/10 k ) = 5.22 ma the load regulation of the ref195 is typically 2.0 ppm/ma, which results in an error of 10.4 ppm (52 v) for the 5.22 ma current drawn from it. this corresponds to a 0.003 lsb error at 8 bits and 0.043 lsb error at 12 bits. bipolar operation using the ad5308/AD5318/ad5328 the ad5308/AD5318/ad5328 have been designed for single- supply operation, but a bipolar output range is also possible using the circuit in figure 16. this circuit will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820, the ad8519, or an op196 as the output amplifier.
rev. 0 e16e ad5308/AD5318/ad5328 1 f v ref abcd v dd v out a 10 f 0.1 f 5v ad820/ ad8519/ op196 5v 5v r1 10k r2 10k sclk sync gnd serial interface v out v in gnd ref192 e5v v out b v out c v out h 6v to 16v v ref efgh ad5308/AD5318/ ad5328 din figure 16. bipolar operation with the ad5308/ AD5318/ad5328 t he output voltage for any input code can be calculated as follows: v out = [( refin d/ 2 n ) ( r 1 + r 2)/ r 1 e refin ( r 2 /r 1)] where: d = the decimal equivalent of the code loaded to the dac n = the dac resolution refin = the reference voltage input with refin = 5 v , r 1 = r 2 = 10 k : v out = (10 d /2 n ) e 5 v opto-isolated interface for process control applications the ad5308/AD5318/ad5328 have a versatile 3-wire serial interface making them ideal for generating accurate voltages in process control and industrial applications. due to noise, safety requirements, or distance, it may be necessary to isolate the ad5308/AD5318/ad5328 from the controller. this can easily be achieved by using opto-isolators that will provide isolation in excess of 3 kv. the actual data rate achieved may be limited by the type of optocouplers chosen. the serial loading structure of the ad5308/AD5318/ad5328 makes them ideally suited for use in opto-isolated applications. figure 17 shows an opto- isolated interface to the ad5308/AD5318/ad5328 where din, sclk, and sync are driven from optocouplers. the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5308/ AD5318/ad5328. v dd sclk 10k v ref abcd din sync v dd gnd v out a 0.1 f 10 f v ref efgh v out b sclk 5v regulator power v dd sync 10k v dd din 10k v out c v out d ad5308/AD5318/ ad5328 v out e v out f v out g v out h figure 17. ad5308/AD5318/ad5328 in an opto-isolated interface decoding multiple ad5308/AD5318/ad5328s the sync pin on the ad5308/AD5318/ad5328 can be used in applications to decode a number of dacs. in this applica- tion, the dacs in the system receive the same serial clock and serial data but only the sync to one of the devices will be active at any one time, allowing access to four channels in this 16-channel system. the 74hc139 is used as a 2-to-4 line decoder to address any of the dacs in the system. to prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded-address inputs are changing state. figure 18 shows a diagram of a typical setup for decoding multiple ad5308 devices in a system. 74hc139 v cc v dd enable coded address 1g 1a 1b dgnd 1y0 1y1 1y2 1y3 sclk din sync din sclk v out a v out b v out g v out h sync din sclk sync din sclk sync din sclk ad5308 v out a v out b v out g v out h v out a v out b v out g v out h v out a v out b v out g v out h ad5308 ad5308 ad5308 figure 18. decoding multiple ad5308 devices in a system
rev. 0 ad5308/AD5318/ad5328 e17e table v. overview of ad53xx serial devices part no. resolution dnl v ref pins settling time interface package pins singles ad5300 8 60.25 0 (v ref = v dd ) 4 s spi sot-23, microsoic 6, 8 ad5310 10 60.50 0 (v ref = v dd ) 6 s spi sot-23, microsoic 6, 8 ad5320 12 61.00 0 (v ref = v dd ) 8 s spi sot-23, microsoic 6, 8 ad5301 8 0.25 0 (v ref = v dd ) 6 s 2-wire sot-23, microsoic 6, 8 ad5311 10 0.50 0 (v ref = v dd ) 7 s 2-wire sot-23, microsoic 6, 8 ad5321 12 1.00 0 (v ref = v dd ) 8 s 2-wire sot-23, microsoic 6, 8 duals ad5302 8 0.25 2 6 s spi microsoic 10 ad5312 10 0.50 2 7 s spi microsoic 10 ad5322 12 1.00 2 8 s spi microsoic 10 ad5303 8 0.25 2 6 s spi tssop 16 ad5313 10 0.50 2 7 s spi tssop 16 ad5323 12 1.00 2 8 s spi tssop 16 quads ad5304 8 0.25 1 6 s spi microsoic 10 ad5314 10 0.50 1 7 s spi microsoic 10 ad5324 12 1.00 1 8 s spi microsoic 10 ad5305 8 0.25 1 6 s 2-wire microsoic 10 ad5315 10 0.50 1 7 s 2-wire microsoic 10 ad5325 12 1.00 1 8 s 2-wire microsoic 10 ad5306 8 0.25 4 6 s 2-wire tssop 16 ad5316 10 0.50 4 7 s 2-wire tssop 16 ad5326 12 1.00 4 8 s 2-wire tssop 16 ad5307 8 0.25 2 6 s spi tssop 16 ad5317 10 0.50 2 7 s spi tssop 16 ad5327 12 1.00 2 8 s spi tssop 16 octals ad5308 8 0.25 2 6 s spi tssop 16 AD5318 10 0.50 2 7 s spi tssop 16 ad5328 12 1.00 2 8 s spi tssop 16 visit www.analog.com/support/standard_linear/selection_guides/ad53xx.html table vi. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time additional pin functions package pins singles buf gain hben clr ad ?? ? ?? ?? ? ?? ? ? ? ?? ? ?? ? ?? ?? ?? ??
rev. 0 e18e ad5308/AD5318/ad5328 outline dimensions 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 coplanarity compliant to jedec standards mo-153ab
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c02812e0e6/02(0) printed in u.s.a. e20e

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